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<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
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<div class="title">xuartns550_l.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:ga58ff500307c70fda263888b18fc6389c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga58ff500307c70fda263888b18fc6389c">XUartNs550_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;Xil_In32((BaseAddress) + (RegOffset))</td></tr>
<tr class="memdesc:ga58ff500307c70fda263888b18fc6389c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read a UART register.  <a href="group__uartns550__v3__3.html#ga58ff500307c70fda263888b18fc6389c">More...</a><br /></td></tr>
<tr class="separator:ga58ff500307c70fda263888b18fc6389c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae648146666080fdac4f6949b6ed3101a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gae648146666080fdac4f6949b6ed3101a">XUartNs550_WriteReg</a>(BaseAddress,  RegOffset,  RegisterValue)&#160;&#160;&#160;Xil_Out32((BaseAddress) + (RegOffset), (RegisterValue))</td></tr>
<tr class="memdesc:gae648146666080fdac4f6949b6ed3101a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Write to a UART register.  <a href="group__uartns550__v3__3.html#gae648146666080fdac4f6949b6ed3101a">More...</a><br /></td></tr>
<tr class="separator:gae648146666080fdac4f6949b6ed3101a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfbf9e5ce401ea4b07a19752802926f7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gacfbf9e5ce401ea4b07a19752802926f7">XUartNs550_GetLineStatusReg</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__uartns550__v3__3.html#ga58ff500307c70fda263888b18fc6389c">XUartNs550_ReadReg</a>((BaseAddress), <a class="el" href="group__uartns550__v3__3.html#ga9cb658f2d8ea9eb438ee626a74ab65ef">XUN_LSR_OFFSET</a>)</td></tr>
<tr class="memdesc:gacfbf9e5ce401ea4b07a19752802926f7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the UART Line Status Register.  <a href="group__uartns550__v3__3.html#gacfbf9e5ce401ea4b07a19752802926f7">More...</a><br /></td></tr>
<tr class="separator:gacfbf9e5ce401ea4b07a19752802926f7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab9ba96c18cb50a8ab5873d781b4ee94e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gab9ba96c18cb50a8ab5873d781b4ee94e">XUartNs550_GetLineControlReg</a>(BaseAddress)&#160;&#160;&#160;<a class="el" href="group__uartns550__v3__3.html#ga58ff500307c70fda263888b18fc6389c">XUartNs550_ReadReg</a>((BaseAddress), <a class="el" href="group__uartns550__v3__3.html#ga50bcaf32aedaf4476931b898961a533f">XUN_LCR_OFFSET</a>)</td></tr>
<tr class="memdesc:gab9ba96c18cb50a8ab5873d781b4ee94e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the UART Line Status Register.  <a href="group__uartns550__v3__3.html#gab9ba96c18cb50a8ab5873d781b4ee94e">More...</a><br /></td></tr>
<tr class="separator:gab9ba96c18cb50a8ab5873d781b4ee94e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4f3ff99ca70dfe6c715cbbfdd9742230"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga4f3ff99ca70dfe6c715cbbfdd9742230">XUartNs550_SetLineControlReg</a>(BaseAddress,  RegisterValue)&#160;&#160;&#160;<a class="el" href="group__uartns550__v3__3.html#gae648146666080fdac4f6949b6ed3101a">XUartNs550_WriteReg</a>((BaseAddress), <a class="el" href="group__uartns550__v3__3.html#ga50bcaf32aedaf4476931b898961a533f">XUN_LCR_OFFSET</a>, (RegisterValue))</td></tr>
<tr class="memdesc:ga4f3ff99ca70dfe6c715cbbfdd9742230"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the UART Line Status Register.  <a href="group__uartns550__v3__3.html#ga4f3ff99ca70dfe6c715cbbfdd9742230">More...</a><br /></td></tr>
<tr class="separator:ga4f3ff99ca70dfe6c715cbbfdd9742230"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga24622c1399f2cbab46e9dda140ef4aa0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga24622c1399f2cbab46e9dda140ef4aa0">XUartNs550_EnableIntr</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga24622c1399f2cbab46e9dda140ef4aa0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the transmit and receive interrupts of the UART.  <a href="group__uartns550__v3__3.html#ga24622c1399f2cbab46e9dda140ef4aa0">More...</a><br /></td></tr>
<tr class="separator:ga24622c1399f2cbab46e9dda140ef4aa0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9039b3a4a9852fa556e522976edd1288"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga9039b3a4a9852fa556e522976edd1288">XUartNs550_DisableIntr</a>(BaseAddress)</td></tr>
<tr class="memdesc:ga9039b3a4a9852fa556e522976edd1288"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the transmit and receive interrupts of the UART.  <a href="group__uartns550__v3__3.html#ga9039b3a4a9852fa556e522976edd1288">More...</a><br /></td></tr>
<tr class="separator:ga9039b3a4a9852fa556e522976edd1288"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga941188ffba023576548effef6ccb0707"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga941188ffba023576548effef6ccb0707">XUartNs550_IsReceiveData</a>(BaseAddress)&#160;&#160;&#160;(<a class="el" href="group__uartns550__v3__3.html#gacfbf9e5ce401ea4b07a19752802926f7">XUartNs550_GetLineStatusReg</a>(BaseAddress) &amp; <a class="el" href="group__uartns550__v3__3.html#ga64e43cf523785c523618adc1f046370f">XUN_LSR_DATA_READY</a>)</td></tr>
<tr class="memdesc:ga941188ffba023576548effef6ccb0707"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if there is receive data in the receiver and/or FIFO.  <a href="group__uartns550__v3__3.html#ga941188ffba023576548effef6ccb0707">More...</a><br /></td></tr>
<tr class="separator:ga941188ffba023576548effef6ccb0707"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabae5b671e19c043af9e1c76e183acb60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gabae5b671e19c043af9e1c76e183acb60">XUartNs550_IsTransmitEmpty</a>(BaseAddress)&#160;&#160;&#160;(<a class="el" href="group__uartns550__v3__3.html#gacfbf9e5ce401ea4b07a19752802926f7">XUartNs550_GetLineStatusReg</a>(BaseAddress) &amp; <a class="el" href="group__uartns550__v3__3.html#gacfc60ddcada499862b482041805b1f03">XUN_LSR_TX_BUFFER_EMPTY</a>)</td></tr>
<tr class="memdesc:gabae5b671e19c043af9e1c76e183acb60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Determine if a byte of data can be sent with the transmitter.  <a href="group__uartns550__v3__3.html#gabae5b671e19c043af9e1c76e183acb60">More...</a><br /></td></tr>
<tr class="separator:gabae5b671e19c043af9e1c76e183acb60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Register Map</div></td></tr>
<tr><td colspan="2"><div class="groupText"><p>Register offsets for the 16450/16550 compatible UART device. </p>
</div></td></tr>
<tr class="memitem:ga0c9f6a9aff7a8753caf9965f3162c2ce"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga0c9f6a9aff7a8753caf9965f3162c2ce">XUN_RBR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET)</td></tr>
<tr class="memdesc:ga0c9f6a9aff7a8753caf9965f3162c2ce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive buffer, read only.  <a href="group__uartns550__v3__3.html#ga0c9f6a9aff7a8753caf9965f3162c2ce">More...</a><br /></td></tr>
<tr class="separator:ga0c9f6a9aff7a8753caf9965f3162c2ce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaaeadf9e35937495ade3ac065a4a6ccbf"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaaeadf9e35937495ade3ac065a4a6ccbf">XUN_THR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET)</td></tr>
<tr class="memdesc:gaaeadf9e35937495ade3ac065a4a6ccbf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit holding register.  <a href="group__uartns550__v3__3.html#gaaeadf9e35937495ade3ac065a4a6ccbf">More...</a><br /></td></tr>
<tr class="separator:gaaeadf9e35937495ade3ac065a4a6ccbf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga270ca9810a3fde617c7fd9f5bc707e6d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga270ca9810a3fde617c7fd9f5bc707e6d">XUN_IER_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x04)</td></tr>
<tr class="memdesc:ga270ca9810a3fde617c7fd9f5bc707e6d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt enable.  <a href="group__uartns550__v3__3.html#ga270ca9810a3fde617c7fd9f5bc707e6d">More...</a><br /></td></tr>
<tr class="separator:ga270ca9810a3fde617c7fd9f5bc707e6d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga36427b607774c1107afd847eb85bc4c9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga36427b607774c1107afd847eb85bc4c9">XUN_IIR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x08)</td></tr>
<tr class="memdesc:ga36427b607774c1107afd847eb85bc4c9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt id, read only.  <a href="group__uartns550__v3__3.html#ga36427b607774c1107afd847eb85bc4c9">More...</a><br /></td></tr>
<tr class="separator:ga36427b607774c1107afd847eb85bc4c9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3d652c8c88fd310239eab927dff43d94"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga3d652c8c88fd310239eab927dff43d94">XUN_FCR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x08)</td></tr>
<tr class="memdesc:ga3d652c8c88fd310239eab927dff43d94"><td class="mdescLeft">&#160;</td><td class="mdescRight">Fifo control, write only.  <a href="group__uartns550__v3__3.html#ga3d652c8c88fd310239eab927dff43d94">More...</a><br /></td></tr>
<tr class="separator:ga3d652c8c88fd310239eab927dff43d94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga50bcaf32aedaf4476931b898961a533f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga50bcaf32aedaf4476931b898961a533f">XUN_LCR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x0C)</td></tr>
<tr class="memdesc:ga50bcaf32aedaf4476931b898961a533f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Control Register.  <a href="group__uartns550__v3__3.html#ga50bcaf32aedaf4476931b898961a533f">More...</a><br /></td></tr>
<tr class="separator:ga50bcaf32aedaf4476931b898961a533f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9046de189f3f0a647fc5c908324f31d9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga9046de189f3f0a647fc5c908324f31d9">XUN_MCR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x10)</td></tr>
<tr class="memdesc:ga9046de189f3f0a647fc5c908324f31d9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem Control Register.  <a href="group__uartns550__v3__3.html#ga9046de189f3f0a647fc5c908324f31d9">More...</a><br /></td></tr>
<tr class="separator:ga9046de189f3f0a647fc5c908324f31d9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9cb658f2d8ea9eb438ee626a74ab65ef"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga9cb658f2d8ea9eb438ee626a74ab65ef">XUN_LSR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x14)</td></tr>
<tr class="memdesc:ga9cb658f2d8ea9eb438ee626a74ab65ef"><td class="mdescLeft">&#160;</td><td class="mdescRight">Line Status Register.  <a href="group__uartns550__v3__3.html#ga9cb658f2d8ea9eb438ee626a74ab65ef">More...</a><br /></td></tr>
<tr class="separator:ga9cb658f2d8ea9eb438ee626a74ab65ef"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga69e96899321d1c793301e52cb4ff7d5b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga69e96899321d1c793301e52cb4ff7d5b">XUN_MSR_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x18)</td></tr>
<tr class="memdesc:ga69e96899321d1c793301e52cb4ff7d5b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem Status Register.  <a href="group__uartns550__v3__3.html#ga69e96899321d1c793301e52cb4ff7d5b">More...</a><br /></td></tr>
<tr class="separator:ga69e96899321d1c793301e52cb4ff7d5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad024e52bf451be70a16217ee15136558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gad024e52bf451be70a16217ee15136558">XUN_DRLS_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x00)</td></tr>
<tr class="memdesc:gad024e52bf451be70a16217ee15136558"><td class="mdescLeft">&#160;</td><td class="mdescRight">Divisor Register LSB.  <a href="group__uartns550__v3__3.html#gad024e52bf451be70a16217ee15136558">More...</a><br /></td></tr>
<tr class="separator:gad024e52bf451be70a16217ee15136558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9923a9e780653084f76cd38f4008d0c5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga9923a9e780653084f76cd38f4008d0c5">XUN_DRLM_OFFSET</a>&#160;&#160;&#160;(XUN_REG_OFFSET + 0x04)</td></tr>
<tr class="memdesc:ga9923a9e780653084f76cd38f4008d0c5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Divisor Register MSB.  <a href="group__uartns550__v3__3.html#ga9923a9e780653084f76cd38f4008d0c5">More...</a><br /></td></tr>
<tr class="separator:ga9923a9e780653084f76cd38f4008d0c5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Enable Register (IER) mask(s)</div></td></tr>
<tr class="memitem:ga283d7f5d44a578ce4ae7f3667ba36908"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga283d7f5d44a578ce4ae7f3667ba36908">XUN_IER_MODEM_STATUS</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga283d7f5d44a578ce4ae7f3667ba36908"><td class="mdescLeft">&#160;</td><td class="mdescRight">Modem status interrupt.  <a href="group__uartns550__v3__3.html#ga283d7f5d44a578ce4ae7f3667ba36908">More...</a><br /></td></tr>
<tr class="separator:ga283d7f5d44a578ce4ae7f3667ba36908"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf385b4925367d2717920845f2880ba47"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaf385b4925367d2717920845f2880ba47">XUN_IER_RX_LINE</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gaf385b4925367d2717920845f2880ba47"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive status interrupt.  <a href="group__uartns550__v3__3.html#gaf385b4925367d2717920845f2880ba47">More...</a><br /></td></tr>
<tr class="separator:gaf385b4925367d2717920845f2880ba47"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8536fc383eb2b08497a576b186547930"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga8536fc383eb2b08497a576b186547930">XUN_IER_TX_EMPTY</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga8536fc383eb2b08497a576b186547930"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter empty interrupt.  <a href="group__uartns550__v3__3.html#ga8536fc383eb2b08497a576b186547930">More...</a><br /></td></tr>
<tr class="separator:ga8536fc383eb2b08497a576b186547930"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae3baa08e218c2f904b1f28ffd06bc527"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gae3baa08e218c2f904b1f28ffd06bc527">XUN_IER_RX_DATA</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gae3baa08e218c2f904b1f28ffd06bc527"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receiver data available.  <a href="group__uartns550__v3__3.html#gae3baa08e218c2f904b1f28ffd06bc527">More...</a><br /></td></tr>
<tr class="separator:gae3baa08e218c2f904b1f28ffd06bc527"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt ID Register (INT_ID) mask(s)</div></td></tr>
<tr class="memitem:ga1770fc9ccf8e1fb1549e53fb83bf2980"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga1770fc9ccf8e1fb1549e53fb83bf2980">XUN_INT_ID_MASK</a>&#160;&#160;&#160;0x0000000F</td></tr>
<tr class="memdesc:ga1770fc9ccf8e1fb1549e53fb83bf2980"><td class="mdescLeft">&#160;</td><td class="mdescRight">Only the interrupt ID.  <a href="group__uartns550__v3__3.html#ga1770fc9ccf8e1fb1549e53fb83bf2980">More...</a><br /></td></tr>
<tr class="separator:ga1770fc9ccf8e1fb1549e53fb83bf2980"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad37ac1583a8e7e9f34530947b89e06fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gad37ac1583a8e7e9f34530947b89e06fe">XUN_INT_ID_FIFOS_ENABLED</a>&#160;&#160;&#160;0x000000C0</td></tr>
<tr class="memdesc:gad37ac1583a8e7e9f34530947b89e06fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Only the FIFOs enable.  <a href="group__uartns550__v3__3.html#gad37ac1583a8e7e9f34530947b89e06fe">More...</a><br /></td></tr>
<tr class="separator:gad37ac1583a8e7e9f34530947b89e06fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">FIFO Control Register mask(s)</div></td></tr>
<tr class="memitem:ga4b16c45a8ec1b6fe90e862d4db5f5558"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga4b16c45a8ec1b6fe90e862d4db5f5558">XUN_FIFO_RX_TRIG_MSB</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:ga4b16c45a8ec1b6fe90e862d4db5f5558"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger level MSB.  <a href="group__uartns550__v3__3.html#ga4b16c45a8ec1b6fe90e862d4db5f5558">More...</a><br /></td></tr>
<tr class="separator:ga4b16c45a8ec1b6fe90e862d4db5f5558"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5b79e08613c8560b6f959a7e99de2914"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga5b79e08613c8560b6f959a7e99de2914">XUN_FIFO_RX_TRIG_LSB</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga5b79e08613c8560b6f959a7e99de2914"><td class="mdescLeft">&#160;</td><td class="mdescRight">Trigger level LSB.  <a href="group__uartns550__v3__3.html#ga5b79e08613c8560b6f959a7e99de2914">More...</a><br /></td></tr>
<tr class="separator:ga5b79e08613c8560b6f959a7e99de2914"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad43092374d907d369cfa0c09bccf39c2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gad43092374d907d369cfa0c09bccf39c2">XUN_FIFO_TX_RESET</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gad43092374d907d369cfa0c09bccf39c2"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset the transmit FIFO.  <a href="group__uartns550__v3__3.html#gad43092374d907d369cfa0c09bccf39c2">More...</a><br /></td></tr>
<tr class="separator:gad43092374d907d369cfa0c09bccf39c2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac547846d9841b9801f6b6cd2c879e881"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gac547846d9841b9801f6b6cd2c879e881">XUN_FIFO_RX_RESET</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gac547846d9841b9801f6b6cd2c879e881"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset the receive FIFO.  <a href="group__uartns550__v3__3.html#gac547846d9841b9801f6b6cd2c879e881">More...</a><br /></td></tr>
<tr class="separator:gac547846d9841b9801f6b6cd2c879e881"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga729d149d84afe79ed69445f8bf6d5101"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga729d149d84afe79ed69445f8bf6d5101">XUN_FIFO_ENABLE</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga729d149d84afe79ed69445f8bf6d5101"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the FIFOs.  <a href="group__uartns550__v3__3.html#ga729d149d84afe79ed69445f8bf6d5101">More...</a><br /></td></tr>
<tr class="separator:ga729d149d84afe79ed69445f8bf6d5101"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab75853d561b5a47735a412acc54b1507"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gab75853d561b5a47735a412acc54b1507">XUN_FIFO_RX_TRIGGER</a>&#160;&#160;&#160;0x000000C0</td></tr>
<tr class="memdesc:gab75853d561b5a47735a412acc54b1507"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both trigger level bits.  <a href="group__uartns550__v3__3.html#gab75853d561b5a47735a412acc54b1507">More...</a><br /></td></tr>
<tr class="separator:gab75853d561b5a47735a412acc54b1507"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Line Control Register(LCR) mask(s)</div></td></tr>
<tr class="memitem:gaa2aa323315e8d4e0265bcb004debc302"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaa2aa323315e8d4e0265bcb004debc302">XUN_LCR_DLAB</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gaa2aa323315e8d4e0265bcb004debc302"><td class="mdescLeft">&#160;</td><td class="mdescRight">Divisor latch access.  <a href="group__uartns550__v3__3.html#gaa2aa323315e8d4e0265bcb004debc302">More...</a><br /></td></tr>
<tr class="separator:gaa2aa323315e8d4e0265bcb004debc302"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac488c0877e5d9195ba6702c5d87bbac1"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gac488c0877e5d9195ba6702c5d87bbac1">XUN_LCR_SET_BREAK</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:gac488c0877e5d9195ba6702c5d87bbac1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Cause a break condition.  <a href="group__uartns550__v3__3.html#gac488c0877e5d9195ba6702c5d87bbac1">More...</a><br /></td></tr>
<tr class="separator:gac488c0877e5d9195ba6702c5d87bbac1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb09446c6f42dc66f5247562cb467b83"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gadb09446c6f42dc66f5247562cb467b83">XUN_LCR_STICK_PARITY</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gadb09446c6f42dc66f5247562cb467b83"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stick Parity.  <a href="group__uartns550__v3__3.html#gadb09446c6f42dc66f5247562cb467b83">More...</a><br /></td></tr>
<tr class="separator:gadb09446c6f42dc66f5247562cb467b83"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a9981c3534734f46ae6a7761c272cd2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga5a9981c3534734f46ae6a7761c272cd2">XUN_LCR_EVEN_PARITY</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga5a9981c3534734f46ae6a7761c272cd2"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = even, 0 = odd parity  <a href="group__uartns550__v3__3.html#ga5a9981c3534734f46ae6a7761c272cd2">More...</a><br /></td></tr>
<tr class="separator:ga5a9981c3534734f46ae6a7761c272cd2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4a5273b5f25d43f994d23adcfaceb06f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga4a5273b5f25d43f994d23adcfaceb06f">XUN_LCR_ENABLE_PARITY</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga4a5273b5f25d43f994d23adcfaceb06f"><td class="mdescLeft">&#160;</td><td class="mdescRight">1 = Enable, 0 = Disable parity  <a href="group__uartns550__v3__3.html#ga4a5273b5f25d43f994d23adcfaceb06f">More...</a><br /></td></tr>
<tr class="separator:ga4a5273b5f25d43f994d23adcfaceb06f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac7f9d8d22514af63f22691f8b0aaee5c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gac7f9d8d22514af63f22691f8b0aaee5c">XUN_LCR_2_STOP_BITS</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:gac7f9d8d22514af63f22691f8b0aaee5c"><td class="mdescLeft">&#160;</td><td class="mdescRight">1= 2 stop bits,0 = 1 stop bit  <a href="group__uartns550__v3__3.html#gac7f9d8d22514af63f22691f8b0aaee5c">More...</a><br /></td></tr>
<tr class="separator:gac7f9d8d22514af63f22691f8b0aaee5c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab8237823909f5df4df1635ffe6c3fd8e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gab8237823909f5df4df1635ffe6c3fd8e">XUN_LCR_8_DATA_BITS</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:gab8237823909f5df4df1635ffe6c3fd8e"><td class="mdescLeft">&#160;</td><td class="mdescRight">8 Data bits selection  <a href="group__uartns550__v3__3.html#gab8237823909f5df4df1635ffe6c3fd8e">More...</a><br /></td></tr>
<tr class="separator:gab8237823909f5df4df1635ffe6c3fd8e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf6444c0fe2141a04caa36c3ceff7e7bc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaf6444c0fe2141a04caa36c3ceff7e7bc">XUN_LCR_7_DATA_BITS</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gaf6444c0fe2141a04caa36c3ceff7e7bc"><td class="mdescLeft">&#160;</td><td class="mdescRight">7 Data bits selection  <a href="group__uartns550__v3__3.html#gaf6444c0fe2141a04caa36c3ceff7e7bc">More...</a><br /></td></tr>
<tr class="separator:gaf6444c0fe2141a04caa36c3ceff7e7bc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac4a2b734e8f1aa8c0935ee3afa8f6a00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gac4a2b734e8f1aa8c0935ee3afa8f6a00">XUN_LCR_6_DATA_BITS</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:gac4a2b734e8f1aa8c0935ee3afa8f6a00"><td class="mdescLeft">&#160;</td><td class="mdescRight">6 Data bits selection  <a href="group__uartns550__v3__3.html#gac4a2b734e8f1aa8c0935ee3afa8f6a00">More...</a><br /></td></tr>
<tr class="separator:gac4a2b734e8f1aa8c0935ee3afa8f6a00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga483bdd6c37b57123fdc2a3da8a74a39f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga483bdd6c37b57123fdc2a3da8a74a39f">XUN_LCR_LENGTH_MASK</a>&#160;&#160;&#160;0x00000003</td></tr>
<tr class="memdesc:ga483bdd6c37b57123fdc2a3da8a74a39f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both length bits mask.  <a href="group__uartns550__v3__3.html#ga483bdd6c37b57123fdc2a3da8a74a39f">More...</a><br /></td></tr>
<tr class="separator:ga483bdd6c37b57123fdc2a3da8a74a39f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa87780e1deb82b5068dc0d4f2c495098"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaa87780e1deb82b5068dc0d4f2c495098">XUN_LCR_PARITY_MASK</a>&#160;&#160;&#160;0x00000018</td></tr>
<tr class="memdesc:gaa87780e1deb82b5068dc0d4f2c495098"><td class="mdescLeft">&#160;</td><td class="mdescRight">Both parity bits mask.  <a href="group__uartns550__v3__3.html#gaa87780e1deb82b5068dc0d4f2c495098">More...</a><br /></td></tr>
<tr class="separator:gaa87780e1deb82b5068dc0d4f2c495098"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Mode Control Register(MCR) mask(s)</div></td></tr>
<tr class="memitem:ga04187396f216eb0cd5be0db172fb1934"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga04187396f216eb0cd5be0db172fb1934">XUN_MCR_LOOP</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:ga04187396f216eb0cd5be0db172fb1934"><td class="mdescLeft">&#160;</td><td class="mdescRight">Local loopback.  <a href="group__uartns550__v3__3.html#ga04187396f216eb0cd5be0db172fb1934">More...</a><br /></td></tr>
<tr class="separator:ga04187396f216eb0cd5be0db172fb1934"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeb40f8130a80ee807ea023a371bf8c38"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaeb40f8130a80ee807ea023a371bf8c38">XUN_MCR_OUT_2</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:gaeb40f8130a80ee807ea023a371bf8c38"><td class="mdescLeft">&#160;</td><td class="mdescRight">General output 2 signal.  <a href="group__uartns550__v3__3.html#gaeb40f8130a80ee807ea023a371bf8c38">More...</a><br /></td></tr>
<tr class="separator:gaeb40f8130a80ee807ea023a371bf8c38"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga73b885722152824dc9a12d643dea0bf5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga73b885722152824dc9a12d643dea0bf5">XUN_MCR_OUT_1</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga73b885722152824dc9a12d643dea0bf5"><td class="mdescLeft">&#160;</td><td class="mdescRight">General output 1 signal.  <a href="group__uartns550__v3__3.html#ga73b885722152824dc9a12d643dea0bf5">More...</a><br /></td></tr>
<tr class="separator:ga73b885722152824dc9a12d643dea0bf5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae4f30ef843108b79b9d582bada19819a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gae4f30ef843108b79b9d582bada19819a">XUN_MCR_RTS</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:gae4f30ef843108b79b9d582bada19819a"><td class="mdescLeft">&#160;</td><td class="mdescRight">RTS signal.  <a href="group__uartns550__v3__3.html#gae4f30ef843108b79b9d582bada19819a">More...</a><br /></td></tr>
<tr class="separator:gae4f30ef843108b79b9d582bada19819a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga3c2e9f72e54de87dedaafe6085ae4ec9"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga3c2e9f72e54de87dedaafe6085ae4ec9">XUN_MCR_DTR</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga3c2e9f72e54de87dedaafe6085ae4ec9"><td class="mdescLeft">&#160;</td><td class="mdescRight">DTR signal.  <a href="group__uartns550__v3__3.html#ga3c2e9f72e54de87dedaafe6085ae4ec9">More...</a><br /></td></tr>
<tr class="separator:ga3c2e9f72e54de87dedaafe6085ae4ec9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Line Status Register(LSR) mask(s)</div></td></tr>
<tr class="memitem:gab923b7cea4222649e9cf8a0a7413ed35"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gab923b7cea4222649e9cf8a0a7413ed35">XUN_LSR_RX_FIFO_ERROR</a>&#160;&#160;&#160;0x00000080</td></tr>
<tr class="memdesc:gab923b7cea4222649e9cf8a0a7413ed35"><td class="mdescLeft">&#160;</td><td class="mdescRight">An errored byte is in FIFO.  <a href="group__uartns550__v3__3.html#gab923b7cea4222649e9cf8a0a7413ed35">More...</a><br /></td></tr>
<tr class="separator:gab923b7cea4222649e9cf8a0a7413ed35"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga648b52ef84c2214179e2fe3c80d77677"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga648b52ef84c2214179e2fe3c80d77677">XUN_LSR_TX_EMPTY</a>&#160;&#160;&#160;0x00000040</td></tr>
<tr class="memdesc:ga648b52ef84c2214179e2fe3c80d77677"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmitter is empty.  <a href="group__uartns550__v3__3.html#ga648b52ef84c2214179e2fe3c80d77677">More...</a><br /></td></tr>
<tr class="separator:ga648b52ef84c2214179e2fe3c80d77677"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacfc60ddcada499862b482041805b1f03"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gacfc60ddcada499862b482041805b1f03">XUN_LSR_TX_BUFFER_EMPTY</a>&#160;&#160;&#160;0x00000020</td></tr>
<tr class="memdesc:gacfc60ddcada499862b482041805b1f03"><td class="mdescLeft">&#160;</td><td class="mdescRight">Transmit holding reg empty.  <a href="group__uartns550__v3__3.html#gacfc60ddcada499862b482041805b1f03">More...</a><br /></td></tr>
<tr class="separator:gacfc60ddcada499862b482041805b1f03"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae74ee94f0c84de4861c57c04bff0d390"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gae74ee94f0c84de4861c57c04bff0d390">XUN_LSR_BREAK_INT</a>&#160;&#160;&#160;0x00000010</td></tr>
<tr class="memdesc:gae74ee94f0c84de4861c57c04bff0d390"><td class="mdescLeft">&#160;</td><td class="mdescRight">Break detected interrupt.  <a href="group__uartns550__v3__3.html#gae74ee94f0c84de4861c57c04bff0d390">More...</a><br /></td></tr>
<tr class="separator:gae74ee94f0c84de4861c57c04bff0d390"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga55e6bddf04ae12aba48d7176dbec9763"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga55e6bddf04ae12aba48d7176dbec9763">XUN_LSR_FRAMING_ERROR</a>&#160;&#160;&#160;0x00000008</td></tr>
<tr class="memdesc:ga55e6bddf04ae12aba48d7176dbec9763"><td class="mdescLeft">&#160;</td><td class="mdescRight">Framing error on current byte.  <a href="group__uartns550__v3__3.html#ga55e6bddf04ae12aba48d7176dbec9763">More...</a><br /></td></tr>
<tr class="separator:ga55e6bddf04ae12aba48d7176dbec9763"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga94c55231673313abf9f38f451bf952b4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga94c55231673313abf9f38f451bf952b4">XUN_LSR_PARITY_ERROR</a>&#160;&#160;&#160;0x00000004</td></tr>
<tr class="memdesc:ga94c55231673313abf9f38f451bf952b4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Parity error on current byte.  <a href="group__uartns550__v3__3.html#ga94c55231673313abf9f38f451bf952b4">More...</a><br /></td></tr>
<tr class="separator:ga94c55231673313abf9f38f451bf952b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga21276c29b98219b18cf86d0eb2c7134b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga21276c29b98219b18cf86d0eb2c7134b">XUN_LSR_OVERRUN_ERROR</a>&#160;&#160;&#160;0x00000002</td></tr>
<tr class="memdesc:ga21276c29b98219b18cf86d0eb2c7134b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Overrun error on receive FIFO.  <a href="group__uartns550__v3__3.html#ga21276c29b98219b18cf86d0eb2c7134b">More...</a><br /></td></tr>
<tr class="separator:ga21276c29b98219b18cf86d0eb2c7134b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga64e43cf523785c523618adc1f046370f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga64e43cf523785c523618adc1f046370f">XUN_LSR_DATA_READY</a>&#160;&#160;&#160;0x00000001</td></tr>
<tr class="memdesc:ga64e43cf523785c523618adc1f046370f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Receive data ready.  <a href="group__uartns550__v3__3.html#ga64e43cf523785c523618adc1f046370f">More...</a><br /></td></tr>
<tr class="separator:ga64e43cf523785c523618adc1f046370f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf2d9f7f1bffd43b92ef31d187f4bcb5e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#gaf2d9f7f1bffd43b92ef31d187f4bcb5e">XUN_LSR_ERROR_BREAK</a>&#160;&#160;&#160;0x0000001E</td></tr>
<tr class="memdesc:gaf2d9f7f1bffd43b92ef31d187f4bcb5e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Errors except FIFO error and break detected.  <a href="group__uartns550__v3__3.html#gaf2d9f7f1bffd43b92ef31d187f4bcb5e">More...</a><br /></td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga39973a1a14e9e66e4bd3a8e90320c982"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga39973a1a14e9e66e4bd3a8e90320c982">XUartNs550_SendByte</a> (UINTPTR BaseAddress, u8 Data)</td></tr>
<tr class="memdesc:ga39973a1a14e9e66e4bd3a8e90320c982"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function sends a data byte with the UART.  <a href="group__uartns550__v3__3.html#ga39973a1a14e9e66e4bd3a8e90320c982">More...</a><br /></td></tr>
<tr class="separator:ga39973a1a14e9e66e4bd3a8e90320c982"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2f885279ade985dee519d1f4c3730b1c"><td class="memItemLeft" align="right" valign="top">u8&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga2f885279ade985dee519d1f4c3730b1c">XUartNs550_RecvByte</a> (UINTPTR BaseAddress)</td></tr>
<tr class="memdesc:ga2f885279ade985dee519d1f4c3730b1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">This function receives a byte from the UART.  <a href="group__uartns550__v3__3.html#ga2f885279ade985dee519d1f4c3730b1c">More...</a><br /></td></tr>
<tr class="separator:ga2f885279ade985dee519d1f4c3730b1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5aa56fa41ef620d2199925f22f2ca21f"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__uartns550__v3__3.html#ga5aa56fa41ef620d2199925f22f2ca21f">XUartNs550_SetBaud</a> (UINTPTR BaseAddress, u32 InputClockHz, u32 BaudRate)</td></tr>
<tr class="memdesc:ga5aa56fa41ef620d2199925f22f2ca21f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the baud rate for the UART.  <a href="group__uartns550__v3__3.html#ga5aa56fa41ef620d2199925f22f2ca21f">More...</a><br /></td></tr>
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